1. Field of the Invention
The present invention relates to semi-conductor devices manufactured according to the technology for forming components or integrated circuits from thin monocrystalline layers of silicon deposited on an insulating substrate. Numerous studies have been made, more especially during the last 15 years or so, to succeed in mastering this technology. The anticipated advantages are, in theory, multiple. The following advantages may for example be mentioned:
The components or circuit parts formed in the thin layer are easily insulated electrically from each other by chemical cutting instead of by using dielectric layers (in general silica) or p/n junctions as is the case for traditional technologies based on solid silicon. The fact of doing away with insulation by a junction considerably increases the resistance to ionizing radiations, by reducing the number of active electron-hole pairs created, which is an essential quality for electronic elements placed in a severe environment.
The parasite connection capacity between active components due to the solid dielectric substrate is very low, thus contributing to the design of rapid logic circuits or ultra high frequency circuits. Moreover, the junction capacities are also eliminated.
The insulating substrate technology is simpler than that using solid monocrystalline silicone. Thus a circuit may be formed by this technology using a procedure which only requires 6 to 8 masking levels; an equilvalent circuit formed in the traditional technology requires 16 to 20 masking levels. Furthermore, the surface gain is estimated at about 30%.
Finally, in structures of the CMOS on solid silicon type, the problemn known under the name of "latch-up effect" that is to say the appearance of a parasite bi polar transistor, may also be eliminated by using an insulating substrate.
2. Description of the Prior Art
In the Prior Art, two types of insulating substrates have been tested: amorphous substrates and monocrystalline substrates. In the first case, the monocrystalline crystalization of the deposited silicon is promoted, either by one or more nuclei or by the definition of a network of parallel lines on the surface of the substrate, imposing a preferential crystallographic orientation (which technique is called "graphoepitaxy").
If the crystallographic orientation is not obtained at the time of depositing, it may be obtained by subsequent treatment: reheating, with or without remelting of the deposited silicon layer for example.
In the state of development of the technology, with this approach monocrystalline zones having an area of a few square millimeters have been obtained. Crystallized zones of a few square centimeters have even been obtained which only comprise sub-joints of nuclei which do not seem to have a determining influence on the electric properties of the material or of the structures formed. This is the case more particularly with the "MOSFET" structures.
In the second case, monocrystalline insulating substrates serve as coherent nuclei for the growth of the layer. This latter is therefore monocrystalline as a whole.
The conditions which the substrates must satisfy are of a physical kind: in particular, crystalline mesh and expansion coefficient close to those of the layer and of a chemical kind: thermo stabiliy and absence of reactivity with a layer and the environment, that is to say more concretely, with the atmosphere reigning in the enclosure of the reactor used for the manufacture.
With a view to growing thin silicon layers, several substrates have been tested such as quartz, spinel, corindon or sapphire. Only this latter has given rise to industrial development. The technology is known under the name "SOS" ("silicon on sapphire"). In fact, although from the point of view of the electric quality of the substratelayer interface, quartz is theoretically preferable, from a crystollographic point of view silicon deposited on quartz is of very poor quality. It appears from experience that corindon is better than (Al.sub.2 O.sub.3 MgO). However, the electric characteristics of "SOS" type structures are mediocre: uncontrolled and thermally unstable doping, low mobility and high interfacial recombination rate. These effects limit the preformances of "SOS" circuits, in particular for bipolar circuits and for ultra high frequency applications. These circuits are only interesting when they are used as so called "hardened" circuits, that is to say insensitive to ionizing radiation.
The mediocre qualities of "SOS" type circuits may be explained by the nature of the alumina-silicon interface. This interface is not perfect from an electric point of view. There exists a high interface state density which modifies the conductivity of the interfacial zone. Low interface charge density, typically less than 10.sup.11 per Cm.sup.2, is desirable. Furthermore, alumina tends to be reduced by the silane in the presence of hydrogen and consequently the silicon layer contains not inconsiderable amounts of aluminium, more or less oxidized, being thus in a substitutional position for the silicon network. Considerations of cost must also be taken into account, for the price of a sapphire substrate is relatively high with respect to the conventional substrate, even if this extra cost is partly offset by the greater simplicity of manufacture of the circuit, as was mentioned above.
From the experience acquired from the above mentioned studies, the following lessons may be drawn: the theoretical advantages of this technology would only be industrially useable if:
the electric properties of the silicon layer correspond to those of the solid material, bounded by two neighboring ideal surfaces; PA1 the steps of traditional technology on solid silicon for obtaining circuits with very high integration densities are applicable within the framework of the technology of depositing on an insulating substrate, without impairing the properties of the solid silicon. PA1 the substrate must be chemically inert with respect to the treatment atmospheres and with respect to the silicon, up to temperatures at least equal to 1050.degree. C. PA1 the expansion coefficient of the substrate, at least in the zone close to the interface, must be matched to that of the silicon, PA1 a silica layer must be created between the deposited silicon layers and the insulating substrate, this silicon-silica interface being, in the present state of knowledge, recognized as one of the only ones ensuring good electric quality.
From the practical point of view, that gives rise to the following requirements:
This latter requirement cannot be fulfilled by a process which consists simply in creating, successively, a continuous silica layer on the insulating substrate in one or more layers of silicon. Under these conditions, the layers and interfaces created would be of mediocre quality, from the crystallographic characteristic and electric points of view.
It is then apparent that the conventional approach used in the Prior Art does not allow these three points to be satisfied simultaneously.
Furthermore, it has been discovered that, during return to the ambient temperature, after heat treatment or plasma treatment, extensive defects appeared during this cooling phase which are essentially due to imperfect matching of the expansion parameters of the substrate and of the silicon.
According to an important aspect of the invention, the step for oxidizing the silicon layer is performed concurrently with cooling of the materials.
The aim of the invention is to satisfy this need and proposes a manufacturing process satisfying these conditions and providing silicon layers of good electric quality, the layer remaining compatible with the rest of the technology on solid silicon and allowing a circuit to be obtained with very high integration density.